Sony HDW-750 Maintenance Manual page 83
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Also See for HDW-750:
- Maintenance manual (442 pages) ,
- Operation manual (420 pages) ,
- Supplemental operation manual (156 pages)
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1-26. Circuit Description
1-26-3. Video Signal System
. Clock signal and timing reference signal processing
Two types of clock signals (74.176 MHz and 46.360 MHz
for HDW-750 or 74.25 MHz and 38.672 MHz for HDW-
750CE) are used in the video system circuit of the DVP-18
board.
The 74.176 MHz (for HDW-750) or 74.25 MHz (for
HDW-750CE) clock is supplied from the camera system
circuit of the DCP-28 board to the DVP-18 board where it
is phase-compensated by the 74M CLOCK DRIVE
(IC101), and is then distributed to the respective ICs. The
46.360 MHz (for HDW-750) or 38.672 MHz (for HDW-
750CE) clock is generated by TG (IC200) of the DVP-18
board as the clock that is synchronous with the frame pulse
supplied from the camera system circuit of the DCP-28
board. The 46.360 MHz (for HDW-750) or 38.672 MHz
(for HDW-750CE) clock is phase-compensated by the
46M CLOCK DRIVE (IC203) and is then distributed to
the respective ICs.
The timing reference signals are generated by TG (IC200)
of the DVP-18 board for the respective ICs, from the frame
pulse and the HD pulse that are supplied from the camera
system circuit of the DCP-28 board. However, the timing
reference signal of the playback video data FIL (IC160) is
supplied from the camera system circuit of the DCP-28
board.
1-67
HDW-750/750CE V1
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