15.3.25 ADC2_BADDR (offset address: 0x68)
Bit
31
Name
ADC2_
BADDR31
R/W
R/W
After reset
0
Bit
23
Name
ADC2_
BADDR23
R/W
R/W
After reset
0
Bit
15
Name
ADC2_
BADDR15
R/W
R/W
After reset
0
Bit
7
Name
ADC2_
BADDR7
R/W
R/W
After reset
0
Bit
Name
31:2
ADC2_BADDR(31:2)
1:0
RFU
CHAPTER 15 AC97U (AC97 UNIT)
30
29
ADC2_
ADC2_
BADDR30
BADDR29
BADDR28
R/W
R/W
0
0
22
21
ADC2_
ADC2_
BADDR22
BADDR21
BADDR20
R/W
R/W
0
0
14
13
ADC2_
ADC2_
BADDR14
BADDR13
BADDR12
R/W
R/W
0
0
6
5
ADC2_
ADC2_
BADDR6
BADDR5
R/W
R/W
0
0
Sets the ADC2 DMA base address
Reserved. Write 0 to these bits. 0 is returned after a read.
User's Manual U14579EJ2V0UM
28
27
ADC2_
ADC2_
BADDR27
BADDR26
R/W
R/W
0
0
20
19
ADC2_
ADC2_
BADDR19
BADDR18
R/W
R/W
0
0
12
11
ADC2_
ADC2_
BADDR11
BADDR10
R/W
R/W
0
0
4
3
ADC2_
ADC2_
BADDR4
BADDR3
BADDR2
R/W
R/W
0
0
Function
26
25
ADC2_
ADC2_
ADC2_
BADDR25
BADDR24
R/W
R/W
0
0
18
17
ADC2_
ADC2_
ADC2_
BADDR17
BADDR16
R/W
R/W
0
0
10
9
ADC2_
ADC2_
ADC2_
BADDR9
BADDR8
R/W
R/W
0
0
2
1
ADC2_
RFU
R/W
R
0
0
24
R/W
0
16
R/W
0
8
R/W
0
0
RFU
R
0
375