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5.3.4
DMAMSKREG (base address + 0x026)
Bit
15
Name
RFU
R/W
R
After reset
0
Bit
7
Name
RFU
R/W
R
After reset
0
Bit
Name
15:4
RFU
3
DMAMSKAIN
2
DMAMSKAOUT
1:0
RFU
This register is used to enable/disable various types of DMA transfers.
The DMA transfer enable bits should be set when the units that receive DMA service have been stopped or when
there are no pending DMA requests. If any of the above bits are set to a unit while a DMA request is pending for that
unit, the operation of the V
84
CHAPTER 5 DCU (DMA CONTROL UNIT)
14
13
RFU
RFU
R
R
0
0
6
5
RFU
RFU
R
R
0
0
Reserved. Write 0 to these bits. 0 is returned after a read.
Audio input DMA transfer enable/disable
1: Enable
0: Disable
Audio output DMA transfer enable/disable
1: Enable
0: Disable
Reserved. Write 0 to these bits. 0 is returned after a read.
4173 will be undefined.
RC
User's Manual U14579EJ2V0UM
12
11
RFU
RFU
RFU
R
R
0
0
4
3
RFU
DMAMSKA
DMAMSKA
IN
OUT
R
R/W
R/W
0
0
Function
10
9
RFU
RFU
R
R
R
0
0
2
1
RFU
RFU
R
R
0
0
8
0
0
0
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